dCUDA: Hardware Supported Overlap of Computation and Communication
(In Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis (SC16), presented in Salt Lake City, Utah, pages 52:1--52:12, IEEE Press, ISBN: 978-1-4673-8815-3, Nov. 2016)
Abstract
Over the last decade, CUDA and the underlying GPU hardware architecture have continuously gained popularity in various high-performance computing application domains such as climate modeling, computational chemistry, or machine learning. Despite this popularity, we lack a single coherent programming model for GPU clusters. We therefore introduce the dCUDA programming model, which implements device-side remote memory access with target notification. To hide instruction pipeline latencies, CUDA programs over-decompose the problem and over-subscribe the device by running many more threads than there are hardware execution units. Whenever a thread stalls, the hardware scheduler immediately proceeds with the execution of another thread ready for execution. This latency hiding technique is key to make best use of the available hardware resources. With dCUDA, we apply latency hiding at cluster scale to automatically overlap computation and communication. Our benchmarks demonstrate perfect overlap for memory bandwidth-bound tasks and good overlap for compute-bound tasks.
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BibTeX
@inproceedings{, author={Tobias Gysi and J. Baer and Torsten Hoefler}, title={{dCUDA: Hardware Supported Overlap of Computation and Communication}}, year={2016}, month={Nov.}, pages={52:1--52:12}, booktitle={Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis (SC16)}, location={Salt Lake City, Utah}, publisher={IEEE Press}, isbn={978-1-4673-8815-3}, source={http://www.unixer.de/~htor/publications/}, }
